The present invention relates to a semiconductor storage device and electronic equipment provided with the device, and relates more concretely to a semiconductor storage device in which field-effect transistors each of which has a memory function body having a function to retain electric charge or polarization and electronic equipment provided with the semiconductor storage device.
As a typical nonvolatile memory used conventionally, a flash memory can be given. FIG. 9A shows a sectional view of a flash memory.
In the flash memory, as shown in FIG. 9A, a gate insulation film 151, a floating gate 152, an insulation film 157 and a word line (control gate) 153 are formed in this order on a semiconductor substrate 150, and a source line 154 and a bit line 155 are formed of a diffusion region on both sides of the floating gate 152, forming a memory cell. An element isolation region 156 is formed around the memory cell.
The symbol shown in FIG. 9B is hereinafter used as the circuit symbol of the flash memory. FIG. 9B shows a control gate 153 that forms the word line, a diffusion region 154 that forms a source line, and a diffusion region 155 that forms a bit line.
FIG. 10 shows a read circuit generally used in the flash memory. Referring to FIG. 10, when the information piece stored in, for example, a memory cell 166m2 is read, the memory cell 166m2 is selectively turned on by making a word line 167m2 go H (High) level. On the other hand, a reference cell 166r is also turned on, and by comparing an output 163m from the memory cell 166m2 via a bit line 168m with an output 163r from the reference cell 166r via a bit line 168r in a sense amplifier 162, the information piece stored in the floating gate of the memory cell 166m2 is read.
It is noted that the reference numerals 165m and 165r denote column selectors, and the reference numerals 164m and 164r denote field-effect transistors (FET's) each of which operates as a load resistance during read.
In general, numbers of memory cells are connected to one bit line for areal reduction. Taking the variations in the characteristics of the memory cells, a noise margin and so on into consideration, the reference cell needs to be accurately set at the desired level in order to execute read without malfunction. Therefore, the reference cell 166r employs an element that has the same configuration and characteristics as those of the memory cells 166m1, 166m2, . . . and is programmed in a state intermediate between a program state and an erase state.
Moreover, it is also desirable to match the capacitance of the bit line extending from the memory cell to the sense amplifier with that of the reference cell to the utmost. Therefore, a technique for making the memory cell and the reference cell share the word line to equalize the number of elements connected to one bit line, a technique for adding a dummy capacitance to a path extending from the reference cell to the sense amplifier and so on are proposed (refer to JP H06-60676 A and JP H06-176583 A).
However, the reference cell has an increased frequency of read relative to that of the memory cell. Therefore, when an element that has the same structure as that of the memory cells 166m1, 166m2, . . . and is programmed in a state intermediate between the program state and the erase state is employed as the reference cell 166r as shown in FIG. 10, a so-called read disturb phenomenon such that not carriers, which have been generated in a small amount at each occasion of voltage application during read to be repeated, have exerted a bad influence on the state of electric charge stored in the floating gate and caused a change in the current level of the reference cell, has been a problem.
The problem of read disturb has been a serious problem particularly when information of more than one bit has been stored in one memory cell, and this has caused a reduction in read speed and read error because a sufficient margin has not been able to be secured between the output from the memory cell and the output from the reference cell.